Effects of mechanical strain on A-Si:H TFT electrical stability

Abstract

As printed transistor and sensor technologies advance, their integration into complex electronic systems becomes possible. Electronic design of such systems requires a systematic approach to simulation and design that takes into account the distinct challenges and opportunities presented by printed devices. In this talk, the speaker will discuss PARC’s approach to circuit design and modeling in the context of building sensor systems in partnership with Thinfilm Electronics based on an ink-jet printed organic TFT process. The electrical stability of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) on flexible substrates is characterized under uniaxial tension and compression applied by bending. TFTs under compression(tension) experience enhanced(reduced) degradation under moderate constant-voltage gate bias (<2MV/cm) compared to without applied strain, with ~5% more(less) reduction in IDS after 104s. After removal of bias stress, TFTs released similar percentages of trapped charge over time regardless of applied strain conditions. The stretched-hyperbola model for defect creation in a-Si:H TFTs was fitted to measurement data and used to predict how applied strain can affect TFT lifetime in practical applications.