Large modulation of carrier transport by grain-boundary molecular packing and microstructure in organic thin films

Abstract

Solution-processable organic semiconductors are of key importance in the development of printed electronics. Performance comparable to that of amorphous silicon has been obtained in polycrystalline films of soluble semiconductors. The otherwise desirable formation of large crystals however, introduces a small number of grain-boundaries in electronic devices resulting in large performance variations, which make applications challenging. Here we engineer the molecular grain-boundary structure of a high-performance n-type semiconductor (PDI8-CN2) to study its effect on transport. We apply advanced X-ray characterization in combination with first-principles calculations and transistor measurements. We find that in PDI8-CN2, which packs with a slip-stacked motif, grain-boundary orientation modulates carrier mobility over two orders of magnitude. As a consequence, in a film where the grain-boundary structure is random, few unfavorable grain-boundaries dominate device performance. Due to the unit cell packing, grain-boundary orientation effects are much reduced in herringbone-stacked materials. This study provides important guidelines for the design of new materials. In summary, we prepared anisotropic films of PDI8-CN2 via a modified drop casting technique. The high angle grain boundaries separating relatively well-aligned domains were found to induce a large in-plane charge transport anisotropy. The poor orbital overlap associated with high angle grain boundaries in slip stacked molecules is speculated to be an underlying cause of the suppressed transport through these grain boundaries. Indeed, by better understanding the nature of the limiting factors in polycrystalline charge transport, engineering decisions can be made with respect to optimizing both device performance and reproducibility. Our work shows that the complete elimination of grain boundaries or, conversely, the introduction of many grain boundaries (as is the case with small grain morphologies) is not necessary for device uniformity. Instead, device performance can be optimized by the controlling grain boundary orientation or reducing the energetic barrier associated with transport across such boundaries.