Scalable logic-addressed memory: printing integration of organic complementary logic and ferroelectric memory

Abstract

The combination of logic and rewritable memory will greatly enhance the functionalities of printed electronics. The addition of addressing logic is necessary for these arrays to be scalable: a binary logic decoder allows 2^N rows in an array to be controlled with just N-bit lines. In addition to scaling memory arrays, the decoder logic is also widely applicable to arrayed sensor and display applications. In this work, we have demonstrated an inkjet-patterned 3-bit decoder for addressing ferroelectric memory capacitors. The all-additive process includes both n- and p-type organic semiconductors, enabling the utilization of complementary logic to reduce power consumption and improve circuit stability. Simulation models are developed for the organic transistors to achieve circuit designs that tolerate the variations in printed devices, as well as to determine the minimum performance requirements for reliable digital logic circuits. The decoder is integrated with ferroelectric memory cells. The combined units are tested by writing values to cells on multiple word lines and bit lines, then reading the all values. The test sequence indicates that each memory cell is properly addressed and is not disturbed by writing and reading of neighboring cells. The fastest timing achieved with this decoder-memory unit is 2 ms setup time. The switching time is in agreement with the simulation results of <2.6 ms. The decoder output level changes less than 3% over a hundred successive repeats of the write-read sequences, with negligible change in slew rates within measurement error. This result verifies that the complementary circuit is stable against bias stress under these conditions. The decoder enables scalability of memory arrays and provides an addressing scheme for matrix arrays common in electronics.