Author: Gooitzen van der Wal
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Low-Power In-Pixel Computing with Current-Modulated Switched Capacitors
We present a scalable in-pixel processing architecture that can reduce the data throughput by 10X and consume less than 30 mW per megapixel at the imager frontend.
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Real-Time Hyper-Dimensional Reconfiguration at the Edge using Hardware Accelerators
In this paper we present Hyper-Dimensional Reconfigurable Analytics at the Tactical Edge using low-SWaP embedded hardware that can perform real-time reconfiguration at the edge leveraging non-MAC deep neural nets (DNN) combined with hyperdimensional (HD) computing accelerators.
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Hyper-Dimensional Analytics of Video Action at the Tactical Edge
We review HyDRATE, a low-SWaP reconfigurable neural network architecture developed under the DARPA AIE HyDDENN (Hyper-Dimensional Data Enabled Neural Network) program.
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Fast, Full Chip Image Stitching of Nanoscale Integrated Circuits
In this paper, we describe the algorithmic steps taken in the processing pipeline to quickly create a global image database of an entire advanced IC.
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FPGA acceleration for feature based processing applications
In this paper, we describe the implementation of an algorithm that combines distributed feature detector (D-HCD) with a rotational invariant feature descriptor (R-HOG).
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An Embedded Vision Services Framework for Heterogeneous Accelerators
This paper describes an architecture framework using heterogeneous hardware accelerators for embedded vision applications.
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Low-Light NV-CMOS Image Sensors for Day/Night Imaging
SRI’s new NV-CMOS™ image sensor technology is designed to capture images over the full range of illumination from bright sunlight to overcast starlight.
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Stereo Vision Embedded System for Augmented Reality
Stereo Vision processing is a critical component of Augmented Reality systems that rely on the precise depth map of a scene to properly place computer generated objects with real life video.
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Multi-Resolution Real-Time Dense Stereo Vision Processing in FPGA
In this paper, we present a low-power, high performance FPGA implementation of a stereo algorithm suitable for embedded real-time platforms.
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A Single Algorithm Combining Exposure and Focus Fusion
This paper proposes an overhauled method of exposure fusion that solves the exposure and focus problems simultaneously, achieving a well-exposed, all-in-focus result.
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Method of Image Fusion and Enhancement Using Mask Pyramid
We proposed an algorithmic approach using a mask pyramid to better localize the selection process. A new embedded system architecture that builds upon the Acadia ® II Vision Processor is proposed.
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Mask Pyramid Methodology for Enhanced Localization in Image Fusion and Enhancement
The proposed approach offers a generic methodology for applications in image enhancement, high dynamic range compression, depth of field extension, and image blending.