Author: Michael A. Isnardi
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Low-Power In-Pixel Computing with Current-Modulated Switched Capacitors
We present a scalable in-pixel processing architecture that can reduce the data throughput by 10X and consume less than 30 mW per megapixel at the imager frontend.
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Real-Time Hyper-Dimensional Reconfiguration at the Edge using Hardware Accelerators
In this paper we present Hyper-Dimensional Reconfigurable Analytics at the Tactical Edge using low-SWaP embedded hardware that can perform real-time reconfiguration at the edge leveraging non-MAC deep neural nets (DNN) combined with hyperdimensional (HD) computing accelerators.
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Hyper-Dimensional Analytics of Video Action at the Tactical Edge
We review HyDRATE, a low-SWaP reconfigurable neural network architecture developed under the DARPA AIE HyDDENN (Hyper-Dimensional Data Enabled Neural Network) program.
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Forensic Prescreening System Using Coded Aperture Snapshot Spectral Imager
We present a camera system for instantaneous, non-destructive capture of spectral signatures for forensic analysis. Our system detects highly probative samples in the forensic scene mixed by the multiple target objects by combining a coded aperture snapshot spectral imager with a multi-spectral detection algorithm.
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Vision Guided Compression on Low-Bit Rate Channels
We introduce Vision Guided Compression (VGC), as a pre-processing technology that can be coupled with standards-based video coding, to provide FMV at low-bit rates.
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Salience-Based Compression: Providing FMV Over Low-Bit Rate Channels
We introduce Salience-Based Compression (SBC), a vision-guided pre-filtering technology, coupled with standards-based video coding.
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H.264 Format/Bitrate/Quality Tradeoff Study
Maximizing transmitted video quality at the highest resolution and highest frame rate is desirable,but multiple approaches can be employed to maximize transmission quality for the video at a given bitrate.
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Reduced Resolution Residual Coding for H.264-Based Compression System
This paper describes a macroblock-based mixed resolution video encoding system. By reducing the spatial resolution of some macroblock residuals intelligently, our preliminary experiments show up to 20% improvement in video compression efficiency compared to H.264.
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A Half D1 MPEG-4 Encoder on the BSP-15 DSP
In this paper, we present the work on implementation of a half-D1interlaced MPEG-4 encoder with Equator Technology DSP chip, BSP-15.
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Spatial Temporal and Histogram Video Registration for Digital Watermark Detection
In this paper, we propose a spatial, temporal and histogram (STH) registration algorithm for video sequences. This algorithm is developed based on a frame-level model of the misalignments often introduced by video processing algorithms, such as compression, frame rate conversion or by video capturing.