Computational sensing-low-power processing publications
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Low-Power In-Pixel Computing with Current-Modulated Switched Capacitors
We present a scalable in-pixel processing architecture that can reduce the data throughput by 10X and consume less than 30 mW per megapixel at the imager frontend.
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Sensor Trajectory Estimation by Triangulating Lidar Returns
The paper describes how to recover the sensor trajectory for an aerial lidar collect using the data for multiple-return lidar pulses.
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Learning with Local Gradients at the Edge
To enable learning on edge devices with fast convergence and low memory, we present a novel backpropagation-free optimization algorithm dubbed Target Projection Stochastic Gradient Descent (tpSGD).
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Real-Time Hyper-Dimensional Reconfiguration at the Edge using Hardware Accelerators
In this paper we present Hyper-Dimensional Reconfigurable Analytics at the Tactical Edge using low-SWaP embedded hardware that can perform real-time reconfiguration at the edge leveraging non-MAC deep neural nets (DNN)…
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Hyper-Dimensional Analytics of Video Action at the Tactical Edge
We review HyDRATE, a low-SWaP reconfigurable neural network architecture developed under the DARPA AIE HyDDENN (Hyper-Dimensional Data Enabled Neural Network) program.
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Bit Efficient Quantization for Deep Neural Networks
In this paper, we present a comparison of model-parameter driven quantization approaches that can achieve as low as 3-bit precision without affecting accuracy.
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Fast, Full Chip Image Stitching of Nanoscale Integrated Circuits
In this paper, we describe the algorithmic steps taken in the processing pipeline to quickly create a global image database of an entire advanced IC.
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BitNet: Bit-Regularized Deep Neural Networks
We present a novel optimization strategy for training neural networks which we call "BitNet". Our key idea is to limit the expressive power of the network by dynamically controlling the…
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Enabling Smart Camera Networks with Smartphone Processors
Distributed smart cameras exploit smartphone processor performance in their node communication and video metadata exchange, allowing the network to collectively reason in interpreting the scene, generating alerts, and making decisions.
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An Embedded Vision Services Framework for Heterogeneous Accelerators
This paper describes an architecture framework using heterogeneous hardware accelerators for embedded vision applications.
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Motion Adaptive Signal Integration-High Dynamic Range (MASI-HDR) Video Processing for Dynamic Platforms
SRI’s MASI-HDR (Motion Adaptive Signal Integration-High Dynamic Range) is a novel technique for generating blur-reduced video using multiple captures for each displayed frame while increasing the effective camera dynamic range…
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Vision Guided Compression on Low-Bit Rate Channels
We introduce Vision Guided Compression (VGC), as a pre-processing technology that can be coupled with standards-based video coding, to provide FMV at low-bit rates.