Novel printing processes for high performance transistors

Abstract

Ink-jet printing has attracted considerable interests as a prototyping and development tool for printed electronics. As more complex printed circuits are being demonstrated, there is a strong demand to improve circuit performance in order to broaden the application space. Besides improving the quality of solution based semiconductor materials, reducing device dimensions will lead to significant advances in circuit speed. The critical dimensions of the transistor structure need to be scaled down in order to achieve high current and minimal parasitic capacitance. This presentation will describe a new approach we recently developed at PARC to print electronic devices and circuits with high resolution. We have designed and printed various devices and logic circuits with improved features and reduced parasitic capacitance. This approach will aid ink-jet printing technology to produce devices with optimized critical dimensions and enable high performance circuits over small areas.